RISC-V extensions and hardware accelerators

ASIC developments are seeing an exponential increasing demand, but the associated design and verification costs are becoming critical. Open-Source RISC-V with Instruction Extensions and dedicated accelerators are expected to be significantly more energy- and cost-efficient solutions than traditional approaches, for several application domains.

The RISC-V architecture defines both the set of instructions (ISA) that can be executed and the most relevant hardware components that support these instructions. RISC-V based platforms address both FPGA and ASIC technologies and can cover a wide range of applications, from the smallest IoT devices to the largest multicore systems for high performance computing.

This activity includes the design of new extensions to the RISC-V ISA and new accelerators aimed at supporting efficiently two families of applications: (i) new cryptographic primitives, selected by the NIST standardization organism to face the threats of quantum computers, and (ii) low-energy AI-enhanced edge applications.

Moreover, RISCV developments for Logic-in-memory applications are investigated.

Finally, Risc-V ISA extensions and loosely coupled accelerators for mixed-precision operations are studied in order to support the implementation of scalable-precision Machine Learning algorithms targeted to better energy efficiency in the context of edge and IoT applications

In the years 2023-2026, the planned activities will be supported by two European projects: TRISTAN and ISOLDE.

Erc Sector:

  • PE7_4 (Micro and nano) systems engineering
  • PE7_5 (Micro and nano) electronic, optoelectronic and photonic components


  • Digital integrated circuits
  • Application specific integrated circuits
  • Artificial Intelligence
  • Cryptography