Circuit architectures: Architectures for probabilistic computing

Probabilistic bits (p-bits), whose description can be achieved by exploiting magnetic devices, are intermediate entities between bits and q-bits.

Bits are deterministic and assume either 0 or 1 values, q-bits show a superposition of 0 and 1 and p-bits are in the middle since they fluctuate between 0 and 1 configurations.

The described characteristic can be obtained by implementing p-bits with low-barrier magnetic tunnel junctions (MTJs), which are spintronic devices for magnetic memory realization.

The p-bits can be connected with a synapse-like interconnection system in order to define a probabilistic spin logic (PLS). In this way, the input applied on each p-bit depends on a bias term and from interconnection with other p-bits.

The main advantages of using magnet technology for this type of simulation are a low time required and power consumption.

The flip of a p-bit is very fast and magnetic devices limit static power consumption. For all the reported reasons, this technology can be employed to perform both Simulated Annealing, directly on a p-bits network and Simulated Quantum annealing.

Erc Sector:

  • PE7_3 Simulation engineering and modelling
  • PE7_4 (Micro and nano) systems engineering
  • PE7_11 Components and systems for applications

Keywords:

  • Probabilistic logic
  • Quantum computing
  • Magnetic devices
  • Random number generator