System-level design via high-level synthesis

The goal of the activity is to explore and expand the use of high-level synthesis in system-level design, in particular for FPGAs. Application domains include hardware acceleration for data center, machine learning and high-performance computing applications. The objective is both to improve performance and to reduce energy consumption, for both large-scale and emebedded applications. The techniques explored include automated implementation of dedicated caches and buffers to speed up DRAM access, as well as global scheduling of multiple accelerators, taking into account resource and memory bandwidth limitations.


ERC Sector:

  • PE7_4 (Micro and nano) systems engineering
  • PE6_2 Computer systems, parallel/distributed systems, sensor networks, embedded systems, cyber-physical systems


  • High level synthesis
  • Field programmable gate arrays
  • Memory architecture
  • System-level scheduling

Research groups