Digital architectures for error correcting codes

This activity focuses on error correcting codes especially for wireless applications and deals with hardware implementation related aspects, including flexibility, high throughput and power consumption. The main error correcting codes analyzed in this activity are turbo codes, low density parity check codes and polar codes.

Currently, we specifically explore the Ultra-reliable low latency communications (URLLC), which combine powerful error correcting capability and low decoding latency. In URLLC, to meet the severe latency constraints, not only a proper selection of the code and related decoding algorithm is necessary, but also an efficient hardware architecture must be conceived for the decoder. The outcome of the activity will be new hardware decoder surpassing the known approaches in terms of error correction capability, latency, and energy-cost efficiency.

The activity is partially supported by the RESTART project, PE_00000001, CUP E13C22001870001(PNRR).

 Link:

ERC Sector:

  • PE7_4 (Micro and nano) systems engineering
  • PE7_6 Communication technology, high-frequency technology
  • PE7_7 Signal processing

Keywords:

  • Very large scale integration
  • Error correction codes

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