In order to reach exascale performance current HPC servers need to be improved. Simple scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development as well as the architecture of the future HPC systems.ECOSCALE tackles this challenge by proposing a scalable programming environment and hardware architecture tailored to the characteristics and trends of current and future HPC applications, reducing significantly the data traffic as well as the energy consumption and delays. We first propose a novel heterogeneous energy-efficient hierarchical architecture and a hybrid MPIOpenCL programming environment and runtime system. The proposed architecture, programming model and runtime system follows a hierarchical approach where the system is partitioned into multiple autonomous Workers (i.e. compute nodes). Workers are interconnected in a tree-like structure in order to form larger Partitioned Global Address Space (PGAS) partitions, which are further hierarchically interconnected via an MPI protocol. Secondly, to further increase the energy efficiency of the system as well as its resilience, the Workers will employ reconfigurable accelerators that can perform coherent memory accesses in the virtual address space utilizing an IOMMU. The ECOSCALE architecture will support shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, and, more importantly, automated hardware synthesis of these resources from an OpenCL-based programming model.We follow a co-design approach that spans a scalable HPC hardware platform, a middleware layer, a programming and a runtime environment as well as a high-level design environment for mapping applications onto the system. A proof of concept prototype and a simulator will be built in order to run two real-world HPC applications and several benchmarks.
WSN-DPCM - WSN DEVELOPMENT, PLANNING AND COMMISSIONING & MAINTENANCE TOOLSET, (2011-2015) - Responsabile Scientifico
UE-funded research - JTI ARTEMIS
Abstract
Despite the considerable research and important advances of the Wireless Sensor Networks (WSN) field, large scale application of the technology is still hindered by technical, complexity and cost issues. Ongoing R&D projects are addressing the shortcomings by focusing on energy harvesting, middleware, network intelligence, standardization, network reliability, adaptability and scalability. These are among the most prominent issues preventing a wider adoption of WSN-based solutions by system integrators and end users. WSN deployment, testing, and maintenance are still challenging the WSN wider use.This project will address the above WSN challenges by developing an integrated platform for smart environments that will comprise a middleware for heterogeneous wireless technologies as well as an integrated engineering tool for quick system development, a planning tool and a commissioning & maintenance tool for expert and non-expert users. This project will build two demonstrators in order to evaluate the impact of the developed middleware and the tools. The first application demonstrator will be an outdoor parking application where WSN will detect free parking slots in an outdoor parking and guide the drivers to reach them, park their car and enter automatically in the system all relevant information. The second application demonstrator will be system where WSN will measure the air quality and noise, light, and electromagnetic levels on city streets to assist the understanding of wide area dynamics and the City Managers' decision making process.This project will contribute to the development of a multi-domain architecture and to provide strategic input to enhance other ARTEMIS application-oriented Sub-Programmes. To further increase the value for the field, most of the project development will be released under a suitable open source license for mutual benefit and to foster academic research and know how to transfer to industry.
The main objective of the COMPLEX project is to increase the competitiveness of the European semiconductor, system integrator and EDA industry by addressing the problem of platform-based design space exploration under consideration of power and performance constraints early in the design process. High performance usually causes high power consumption. A main challenge in today's embedded system design is to find the perfect balance between performance and power. This balance can not be found efficiently and at high quality, because until now no generic framework for accurately and jointly estimating performance and power consumption starting at the algorithmic level is available. This can only be achieved in cooperation on a European level, taking into account European platform providers, system developers/integrators, EDA companies, Universities and research institutes from both, the HW and the embedded SW world.<br/>The COMPLEX project will enable the European semiconductor and electronic system industry to achieve a break through in product quality through substantially improved performance and power efficiency. This quantum leap will be achieved by a new design environment for platform-based design-space exploration offering developers of next-generation mobile and embedded systems a highly efficient and productive design methodology and tool chain allowing them to iteratively explore and refine their applications to meet market requirements. The design technology in particular enables the fast simulation and assessment of the platform at Electronic System Level (ESL) with up to cycle accuracy at the earliest instant in the design process. Several new modelling, exploration and simulation concepts will be developed and combined with well established ESL synthesis, cross-compilation, analysis and simulation tools into a seamless holistic design flow enabling performance &amp; power aware virtual prototyping from a combined hardware-software perspective.
Countries
Francia
Belgio
Paesi Bassi
Italia
Spagna
Cina
Germania
Institutes/Companies
THALES SIX GTS FRANCE SAS
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
EUROPEAN ELECTRONIC CHIPS &amp; SYSTEMS DESIGN INITIATIVE
NXP SEMICONDUCTORS NETHERLANDS BV
EDALab srl
MAGILLEM DESIGN SERVICES SAS
POLITECNICO DI TORINO
POLITECNICO DI MILANO
UNIVERSIDAD DE CANTABRIA
SNPS BELGIUM NV
STMICROELECTRONICS (BEIJING) R&amp;D CO LTD
STMICROELECTRONICS SRL
ChipVision Design Systems AG
GMV AEROSPACE AND DEFENCE SA
Departments
Dipartimento di Automatica Informatica
Dipartimento di Elettronica
MODERN-MODELING AND DESIGN OF RELIABLE, PROCESS VARIATION-AWARE NANOELECTRONIC DEVICES, CIRCUITS AND SYSTEMS, (2009-2012) - Responsabile Scientifico
The influence of process variations is becoming extremely critical for nanoCMOS technology nodes, due to geometric tolerances and manufacturing non-idealities (such as edge or surface roughness, or the fluctuation of the number of doping atoms). As a result, production yields and figures of merit of a circuit such as performance, power, and reliability have become extremely sensitive to uncontrollable statistical process variations. Although some kind of variability has always existed and been taken into account for designing integrated circuits, the largest impact of variability and the greater influence of random or spatial aspects are setting up a completely new challenge. On top of those difficulties, the deficiency of design techniques and EDA methodologies for tackling PVs makes that challenge even more critical.The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.Specifically, the main goals of the project are:1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures.2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performances. - Reliability, noise, EMC/EMI. - Timing, power and yield.3. Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.4. Validation of the modeling and design methods and tools on a variety of silicon demonstrators.The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between industry and research institutes.
Countries
Spagna
Danimarca
Austria
Francia
Svizzera
Grecia
Italia
Paesi Bassi
Germania
Regno Unito
Institutes/Companies
Elastic Clocks S.L.
TEKLATECH A/S
TECHNISCHE UNIVERSITAET WIEN
Tiempo
TECHNISCHE UNIVERSITAET GRAZ
INFINEON TECHNOLOGIES AUSTRIA AG
STMICROELECTRONICS CROLLES 2 SAS
CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA - RECHERCHE ET DEVELOPPEMENT
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Europe has a strong leadership in the domains of intelligent communications, multimedia, and automotive systems. However, the exponential increase in complexity threatens the European competitiveness. Current challenges when designing mixed HW/SW embedded systems are (1) mastering the complexity of the integration between the HW and the SW parts, (2) shortening time-to-market, and (3) reducing design cost. Codesign is the next big step in the holistic ( design of embedded electronic systems; hence it is an essential enabling technology for solving these challenges. It formalizes the interface between the hardware and software parts, and improves the amount of re-use, by allowing one to design models that can be adapted to several different performance/power/cost requirements and to different interface protocols. OSMOSIS will develop a key component required to maintain and enforce the European competitiveness in the intelligent system domains: create an open-source codesign framework for top-down embedded system design. This goal is achieved by joining the numerous on-going efforts in industry and academia into a unified best-practice, industrial-quality framework that will enable an easier transition from research results to industrial exploitation. The OSMOSIS platform will enable experimentation with codesign algorithms, starting from languages such as SystemC and producing HW and SW implementations. The results of the project will have a significant impact on intelligent embedded systems design by promoting cost-efficient software and hardware integration and reducing software/hardware concurrent development time. The consortium mobilizes a significant European force that covers the whole chain of embedded systems design: three embedded system design companies and silicon platform providers an arising research and development centre one of the largest European R&D centres and one prominent academic institution.
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