HEAP - Highly Efficient Adaptive multi-Processor framework

Writing parallel code has traditionally been considered a difficult task, even when it is taken into account from the beginning. At the same time, while processor architecture tends to be relatively standard across applications within a domain, huge performance and power improvements can be achieved by tailoring the cache architecture, to the application at hand.

The HEAP project faces these challenges directly, by providing an innovative toolset that helps software developers profile and parallelize an existing sequential implementation, by exploiting top-level pipeline-style parallelism.

Class International project
Status Completed (31/12/2012)
Type European Research Projects
FP7-ICT
Lenght 33 months
Management

STMicroelectronics SRL (Italy)

Partners
  • STMicroelectronics SRL (Italy)
  • Thales Communications SA (France)
  • Ace Associated Compiler Experts B.V. (Nederland)
  • Synelixis Lyseis Pliroforikis Automatismou & Tilepikoinonion Monoprosopi Epe (Greece)
  • Compaan Design BV (Nederland)
  • Universita degli Studi di Genova (Italy)
  • Athena Research and Innovation Center in Information Communication & Knowledge Technologies (Greece)
  • Politecnico di Torino (Italy)
  • Singkioular Lotzik Anonymos Etairia Pliroforiakon Systimaton & Efarmogon (Greece)
Budget 3.3 millions €
Web site HEAP project website