Stefano Grivet-Talocia receives a Strategic Research Grant from Intel

Intel has recently awarded an SRS (Strategic Research Segment) Grant to Prof. Stefano Grivet-Talocia and his research team at the Department of Electronics and Telecommunications (DET), Politecnico di Torino. This grant has been awarded for the third consecutive year, to foster collaborative research on Electronic Design Automation (EDA) of future high-performance multicore processors and systems. The main objective is the electrical performance verification of entire platforms for High Performance Computing (HPC) and Artificial Intelligence (AI) based on high-end multicore processors, via numerical simulation. The extreme complexity of such systems makes a direct approach infeasible, and creative solutions are urgently needed for an effective and robust design process.

The expertise of Prof. Grivet-Talocia's group in Model Order Reduction (MOR) and behavioral modeling has been leveraging the development of a framework that is capable of speeding up such simulations by at least three orders of magnitude with respect to commercial circuit simulation codes. Power Integrity verification at the system level thus becomes feasible both in a concept phase, when multiple configurations are assessed to select the best option to be designed, and even in a final post-layout setting, when the design is complete and needs to be approved for production.

Prof. Grivet-Talocia says: "I am very proud of this prestigious recognition by a leading semiconductor company. In fact, most of the credit should go to my research team and in particular to my students Antonio Carlucci and Alessandro Moglia, whose work enabled most of the results that we have been accomplishing under this project. Collaborating with Intel is very exciting: we are exposed to the latest (and future) technologies, having the opportunity to conduct theoretical research with an immediate practical application and impact on the market."

Dr. Kaladhar Radhakrishnan (Intel Fellow) states: "I'm extremely impressed with the expertise shown by Prof. Grivet-Talocia and his team in coming up with an efficient way to analyze complex power delivery architectures. The innovative model order reduction techniques developed by the team has enabled the analysis of problems that were previously too vast for conventional SPICE-based solvers to tackle. We are pleased with the results and actively working to make this part of the standard Power Integrity verification flow."